By Topic

DRAM Yield Analysis and Optimization by a Statistical Design Approach

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Yan Li ; Lehrstuhl Tech. Elektron., Tech. Univ. Munich, Munich, Germany ; Schneider, H. ; Schnabel, F. ; Thewes, R.
more authors

In this paper the electric yield of DRAM core circuits is investigated by means of a statistical approach that incorporates a hierarchical linear Gaussian model for the DRAM core sensing process and a lognormal distribution model for the DRAM cell leakage. Analytical yield expressions are obtained and found to be dominated by two independent sources-either the lognormal distribution of the cell leakage components or the Gaussian distribution depending on the array structural parameters, parasitic, and the sense amplifier offset voltage. Analytical yield analysis is conducted for several different DRAM architectures and compared to measurements from signal margin analysis and data retention tests. The yield model is found to be very accurate. Thanks to the short computation time, it can be easily applied to the analysis and yield optimization of novel array structures, DRAM cell leakage analysis, sense amplifier offset voltage requirements, and core supply voltage optimization. It also paves the way for the design for yield of other memory circuits.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:58 ,  Issue: 12 )