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As the gate length of CMOS processes has become smaller and the device fT has increased, applications such as CMOS power amplifiers in the millimeter-wave region have become feasible and practical. This paper describes the development of an empirical large-signal model for sub-100 nm CMOS transistors and demonstrates its successful use in the design of a 4-stage 60 GHz CMOS power amplifier with measured performance of 20 dB gain, +10.3 dBm P1dB, 13.5 dBm Psat and 13% PAE. A novel drain-source current formulation is used, accurately modeling both strong-inversion and sub- threshold characteristics of short-channel, 90 nm CMOS transistors. Further model enhancement is obtained through optimization for millimeter-wave applications using an optimized parasitic extraction process as well as the incorporation of size scalability and temperature dependency, making this modeling approach highly robust.