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A unified VLSI architecture for decomposition and synthesis of discrete wavelet transform

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3 Author(s)
Ming-hwa Sheu ; Dept. of Electron. Eng., Nat. Yunlin Inst. of Technol., Taiwan, China ; Ming-Der Shieh ; Shun-Fa Cheng

This paper presents a unified VLSI architecture that can perform either Discrete Wavelet Transform (DWT) or inverse DWT (IDWT). Based on the Distributed Arithmetic method, an elementary computing module is designed, and used to construct the unified architecture. This architecture has the characteristics of no multiplier, lower hardware cost, shorter latency, higher throughput rate, and regular structure for VLSI implementation. Finally,the architecture is implemented into a single chip based on 0.8 μm CMOS technology. The chip area is 5100*5900 μm2

Published in:

Circuits and Systems, 1996., IEEE 39th Midwest symposium on  (Volume:1 )

Date of Conference:

18-21 Aug 1996