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Low power circuit techniques for fast carry-skip adders

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3 Author(s)
Gayles, E.S. ; Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA ; Omens, R.M. ; Irwin, M.J.

A multi-level carry-skip addition scheme for static CMOS is presented which has O(lg n) asymptotic delay and has speed comparable to a carry-lookahead approach for typical operand bit precisions. However, the proposed architecture results in adders which dissipate nearly half the power of carry-lookahead adders. The proposed carry-skip method is also conflict free. This paper describes the proposed architecture and its circuit implementation, as well as the architecture's asymptotic worst case delay analysis. Also, empirical results comparing the adder's performance with other conventional architectures in a 0.5 μm CMOS process are provided

Published in:

Circuits and Systems, 1996., IEEE 39th Midwest symposium on  (Volume:1 )

Date of Conference:

18-21 Aug 1996

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