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An orthotropic stress field was observed in the vicinity of the Cu-filled TSV on nominal (100) silicon substrate from both μRaman measured data and validated FEM result. The orthotropic elastic behavior of silicon in the (100) plane is believed to be the reason. The FEM model was further validated by the comparison with the measured electrical data, and used to predict the device performance shift under the influence of the TSV-induced stress. The performance shift pattern also showed an orthotropic pattern. This finding has profound implication on 3D silicon stacking design rule and system integration.