Referenced Items are not available for this document.
This brief addresses the problem of clock generation and distribution in globally synchronous locally synchronous chips. A novel architecture of clock generation based on network of coupled all-digital PLLs is proposed. Solutions are proposed to overcome the issues of stability and undesirable synchronized modes (modelocks) of high-order bidirectional PLL networks. The VLSI implementation of the network is discussed in CMOS65 nm technology and the simulation results prove the reliability of the global synchronization by the proposed method.
Published in:
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
Date of Conference: 15-18 May 2011
- Page(s):
- 2589 - 2592
- ISSN :
- 0271-4302
- E-ISBN :
- 978-1-4244-9472-9
- Print ISBN:
- 978-1-4244-9473-6
- INSPEC Accession Number:
- 12436324
- Conference Location :
- Rio de Janeiro
- Digital Object Identifier :
- 10.1109/ISCAS.2011.5938134
- Product Type:
- Conference Publications
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