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A reconfigurable baseband processor for wireless OFDM synchronization sub-system

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3 Author(s)
Mahmoud Abdelall ; Center for Wireless Studies, Faculty of Engineering, Cairo University, Egypt ; Ahmed F. Shalash ; Hossam A. H. Fahmy

In this paper, an Application Specific Instruction-set Processor (ASIP) architecture to perform all OFDM synchronization tasks is proposed. While applicable to many OFDM systems, the proposed architecture is tested on Long Term Evolution (LTE Rel. 8) and WiMAX 802.16e systems. The synchronization tasks include, but not limited to symbol timing, fine carrier frequency offset (CFO) estimation, coarse CFO estimation, cell search, residual CFO estimation and sampling clock frequency offset estimation. The engine is scalable and runs at 120 MHz with a total gate count of 118k and control overhead less than 10% of total processing cycles. The results of software simulations as well as the results of verilog synthesis are presented.

Published in:

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

Date of Conference:

15-18 May 2011