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The design, simulation and optimization of complex continuous-time (CT) circuits like Sigma-Delta modulators require large computation times when using only transistor-level analog simulators like CADENCE Spectre or PSpice. Effective high-level system modeling should be considered in order to reduce the conception effort. However, the closed-loop architecture characteristics and technology requirements should be strictly observed on the respective models. In this work, we present a design methodology and the resulted application tools implying the extraction of CADENCE schematics for analog elements into robust macro-models for MATLAB-SIMULINK and VHDL-AMS. Upon designer's choice, the resulted macro models can be used to implement and optimize a whole modulator in the SIMULINK object-oriented environment or the code-based analog VHDL process. Using the proposed methodology, fast simulations of a sixth-order CT Sigma-Delta modulator have been performed.