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Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes

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3 Author(s)
Yang Sun ; Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX, USA ; Guohui Wang ; Cavallaro, J.R.

We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered decoding algorithm, the block-rows of the parity check matrix are processed sequentially, or layer after layer. The maximum number of rows that can be simultaneously processed by the conventional layered decoder is limited to the sub-matrix size. To remove this limitation and support layer-level parallelism, we extend the conventional layered decoding algorithm and architecture to enable simultaneously processing of multiple (K) layers of a parity check matrix, which will lead to a roughly K-fold throughput increase. As a case study, we have designed a double-layer parallel LDPC decoder for the IEEE 802.11n standard. The decoder was synthesized for a TSMC 45-nm CMOS technology. With a synthesis area of 0.81 mm2 and a maximum clock frequency of 815 MHz, the decoder achieves a maximum throughput of 3.0 Gbps at 15 iterations.

Published in:

Circuits and Systems (ISCAS), 2011 IEEE International Symposium on

Date of Conference:

15-18 May 2011