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Thermal-aware energy minimization of 3D-stacked L3 cache with error rate limitation

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3 Author(s)
Woojin Yun ; Department of Electrical Engineering, KAIST, Daejeon, Republic of Korea ; Kyungsu Kang ; Chong-Min Kyung

Three-dimensional (3D) memory stacking, which enables stacking memory on top of a microprocessor or chip-multiprocessor (CMP), is one of the most promising applications of 3D integration technology to meet memory bandwidth challenges. However, the high power density, i.e., power dissipation per unit volume due to the high integration incurs temperature-related problems such as reliability of 3D-stacked memory. Error correcting codes (ECCs) are commonly used to deal with soft errors and thereby enhance system reliability. In this paper, we present the effects of temperature, refresh period, and ECC policy on the reliability and power consumption of 3D-stacked embedded DRAM (eDRAM). To minimize the energy consumption of the 3D-stacked eDRAM without violating error rate limitation, refresh period and ECC policy must be controlled in a temperature-aware manner. Experimental results show that the proposed adaptive ECC policy with varying temperature achieves a reduction of energy consumption by up to 26% compared with fixed ECC policy under a given error rate constraints.

Published in:

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

Date of Conference:

15-18 May 2011