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We report on the design of a prototype IC called FPDR90 dedicated for readout of hybrid pixel semiconductor detectors used for X-ray imaging applications. The FPDR90 has dimensions of 4 mm × 4 mm and was designed in CMOS 90 nm technology with 9 metal layers. The core of the IC is a matrix of 40×32 pixels with 100 μm ×100 μm pixel size. Each pixel contains a fast charge sensitive amplifier (CSA), a main amplifier stage, two discriminators and two 16-bit ripple counters. The data from pixel matrix are read out via a single LVDS output with 200 Mbps rate. Each pixel contains about 1800 transistors and has a static power consumption of 42 μW for nominal bias condition. The effective pulse shaping for nominal bias condition is 28 ns and the equivalent noise charge is only 106 e- rms (when the CSA connected to silicon pixel detector). In a high gain mode an average gain of the front-end electronics is 64 μV/e-. The effective offset spread (at the one sigma level) from pixel to pixel and with enabled trim DAC is only 0.76 mV (calculated to the CSA input it is only 12 e- rms). The maximum count rate per pixel depends on the effective CSA feedback resistance and the dead time in the front-end as low as 117 ns (paralyzable model) can be set. The FPDR90 can operate with two energy thresholds in the readout mode separate from exposure or in the continuous readout mode with both a single threshold.