By Topic

FPGA Implementation of an ASIP for high throughput DFT/DCT 1D/2D engine

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Hassan, H.M. ; Center for Wireless Studies, Cairo Univ., Cairo, Egypt ; Shalash, A.F. ; Mohamed, K.

In this paper, A novel architecture of an Application Specific Instruction Processor (ASIP) for scalable DFT/IDFT DCT/IDCT ID (N-point) and 2D (N × M point) engine is proposed. An in place configurable radix 2/3/4 butterfly, makes possible the implementation of two radix N/M is varied in the form of 2x × 3y. Therefore the engine can support different communication and signal processing applications. A new address generator scheme is proposed which achieves conflict-free memory access. This scheme is based on partitioning the memory to 4 dual-port memory banks with a continuous address generator to accommodate high-speed requirements. Using same reduction techniques, the twiddle factors memory size is reduced to 28%. By taking advantage of programmability, the engine provides more configurability and flexibility in switching between modes in run-time. Moreover it can be easily adapt to new applications. The DFT/DCT engine requires only 1280 clock cycles for a 1024-point DFT-1D and runs at 120 MHz with SQNR 75.2 dB.

Published in:

Circuits and Systems (ISCAS), 2011 IEEE International Symposium on

Date of Conference:

15-18 May 2011