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Abstract-A clock mesh network synthesis and optimization flow is proposed which entails the optimal mesh size selection, incremental register placement, mesh reduction and buffer driver insertion. The proposed method is based on incrementally placing the registers on a mesh, which gives the method its name "Register on MEsh (ROME)". The primary objectives of ROME are low global clock skew and power dissipation, which are achieved through a sparse mesh implementation with registers mesh. Experimental results show that the total wirelength on the clock mesh (grid wires and stub wires) is reduced by 36.1% with a 2.8ps clock skew improvement. The total power consumption of the experimented circuits is reduced by 14.1% on average.