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P2E-DWT: A parallel and pipelined efficient VLSI architecture of 2-D Discrete Wavelet Transform

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2 Author(s)
Ghantous, M. ; Center for Adv. Comput. Studies, Univ. of Louisiana at Lafayette, Lafayette, LA, USA ; Bayoumi, M.

Discrete Wavelet Transforms has surpassed its counterparts due to its attractive properties, and hence been adopted by image processing algorithms. However, with the emergence of real-time resource constrained embedded imaging platforms, DWT manifests as a bottleneck. This article presents a hardware implementation for 2-D DWT. An area-efficient, parallel and pipelined architecture is proposed with a modified image scan coupled with "multiplier-free" multiplications. Through simulations and implementation, the proposed scheme proves to be a fast, area and power efficient solution for DWT.

Published in:

Circuits and Systems (ISCAS), 2011 IEEE International Symposium on

Date of Conference:

15-18 May 2011