We are currently experiencing intermittent issues impacting performance. We apologize for the inconvenience.
By Topic

Analysis of random capacitor mismatch errors in pipeline analog-to-digital converters

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Nikandish, G. ; Dept. of Electr. Eng., Sharif Univ. of Technol., Tehran, Iran ; Medi, A.

A new modeling and analysis of the nonlinearities caused by the capacitor mismatch errors in the pipeline analog- to-digital converters (ADCs) is presented. Error in each stage is modeled by an input-referred gain error and a nonlinear term. A method is proposed for calculation of the ADC integral nonlinearity (INL) from the total input referred error. Analytical expressions for estimation of the ADC INL in terms of standard deviation of random capacitor mismatch errors are derived. The proposed model is verified by system-level Monte Carlo simulations.

Published in:

Circuits and Systems (ISCAS), 2011 IEEE International Symposium on

Date of Conference:

15-18 May 2011