By Topic

Comparator-based switched-capacitor pipelined ADC with background offset calibration

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Ji-Eun Jang ; Information and Communications Research Laboratories, Industrial Technology Research Institute, Hsinchu, Taiwan

A background offset calibration technique for a comparator-based switched-capacitor (CBSC) circuit is proposed. The calibration circuitry employs a dynamic latch to determine an offset and an auxiliary differential input pair to cancel the offset. Since the proposed technique does not require additional auto-zeroing or offset detecting periods, it is suitable for high-speed low-power operations. A prototype 10-bit 100- MS/s pipelined CBSC ADC is designed and simulated in a 0.13μm CMOS process. Post-layout simulation results show the prototype ADC achieves 9.5 ENOB with a 25.4-MHz sinusoidal input signal and power consumption is 5.9 mW.

Published in:

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

Date of Conference:

15-18 May 2011