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A dense 45nm half-differential SRAM with lower minimum operating voltage

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5 Author(s)
Chen, G. ; Univ. of Michigan, Ann Arbor, MI, USA ; Wieckowski, M. ; Daeyeon Kim ; Blaauw, D.
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We present a 45 nm half-differential 6T SRAM (HD-SRAM) with differential write and single-ended read, enabling asymmetric sizing and VTH selection. The HD-SRAM bitcell uses SRAM physical design rules to achieve the same area as a commercial differential 6T SRAM (D-SRAM). We record measurements from 80 32 kb SRAM arrays. HD-SRAM is 18% lower energy and 14% lower leakage than D-SRAM. It has a 72 mV-lower VMIN, demonstrating higher stability.

Published in:

Circuits and Systems (ISCAS), 2011 IEEE International Symposium on

Date of Conference:

15-18 May 2011