By Topic

Design optimization of an output capacitor-less low dropout regulator with compensation capcitance reduction and slew-rate enhancement technique

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Ho, E.N.Y. ; Dept. of Electron. & Comput. Eng., Hong Kong Univ. of Sci. & Technol., Hong Kong, China ; Mok, P.K.T.

Design optimization methodology of an output capacitor-less low-dropout regulator with small internal compensation capacitance for on-chip application with slew-rate enhancement circuit is presented in this paper. The on-chip compensation capacitance is reduced down to 1.5pF. The idea has been modeled and fabricated in a standard 0.35μm CMOS process. From experimental results, with minimum dropout voltage of 0.2V and 30μA quiescent current, the regulator implemented can operate with supply voltage from 2.4V to 3.3V at maximum loading current of 100mA.

Published in:

Circuits and Systems (ISCAS), 2011 IEEE International Symposium on

Date of Conference:

15-18 May 2011