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A low power high speed envelope detector for serial data systems in 45nm CMOS

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4 Author(s)
Seth, S. ; Texas Instrum., Bangalore, India ; Thinakaran, R. ; Chakravarty, S. ; Sinha, V.

A low power, high speed (480 Mbps) envelope detector for serial data systems such as USB2.0 is presented in this paper. The proposed architecture is based on a high frequency rectifier implementation along with a comparator and offers about 50% power and area saving compared to prior implementations using multiple comparators. A calibration scheme to make the envelope detector process, voltage and temperature independent is discussed. This architecture can be used for any high frequency serial interface requiring envelope detection. The circuit is implemented in 45 mn CMOS technology and consumes 2.5 mW power and occupies 0.015 mm2 area.

Published in:

Circuits and Systems (ISCAS), 2011 IEEE International Symposium on

Date of Conference:

15-18 May 2011