By Topic

A parallel neural network emulator based on application-specific VLSI communication chips

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
M. Schwarz ; Fraunhofer Inst. of Microelecton. Circuits, Duisberg, Germany ; B. J. Hosticka ; M. Kesper ; M. Scholles

This work describes a parallel neural network emulator which combines use of application-specific VLSI communication processors and standard DSPs as programmable processing elements. Locally interconnected communication processors attached to each DSP can span up to 2D- or 3D-grids containing large number of computing nodes and thus form highly parallel multiprocessor networks capable of global pipelined packet switched routing. The use of standard DSPs as processing elements enables the emulation of different types of neurons. These include biologically inspired models with learnable synaptic weights and delays, variable neuron gain, and static and dynamic thresholding. We describe applications of the emulator that include neural robot control as well as temporal signal processing, e.g. beamforming

Published in:

Microelectronics for Neural Networks and Fuzzy Systems, 1994., Proceedings of the Fourth International Conference on

Date of Conference:

26-28 Sep 1994