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RAN2SOM: a reconfigurable neural network architecture based on bit stream arithmetic

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3 Author(s)
M. Gschwind ; Inst. fur Tech. Inf., Tech. Univ. Wien, Austria ; V. Salapura ; O. Maischberger

We introduce the RAN2SOM (Reconfigurable Architecture Neural Networks with Serially Operating Multipliers) architecture, a neural net architecture with a reconfigurable interconnection scheme based on bit stream arithmetic. RAN2SOM nets are implemented using field programmable gate array logic. By conducting the training phase in software and executing the actual application in hardware, conflicting demands can be met: training benefits from a fast edit-debug cycle, and once the design has stabilized a hardware implementation results in higher performance. While neural nets have been implemented in hardware in the past, larger digital nets have not been possible due to the real-estate requirements of single neutrons. We present a bit-serial encoding scheme and computation model, which allows space-efficient computation of the sum of weighted inputs, thereby facilitating the implementation of complex neural networks

Published in:

Microelectronics for Neural Networks and Fuzzy Systems, 1994., Proceedings of the Fourth International Conference on

Date of Conference:

26-28 Sep 1994