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Digital processing compensation mechanisms for highly efficient transmitter architectures

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4 Author(s)
Gilabert, P.L. ; Dept. of Signal Theor. & Commun., Univ. Politec. de Catalunya (UPC), Barcelona, Spain ; Montoro, G. ; Vizarreta, P. ; Berenguer, J.

This article presents the design and final field programmable gate array (FPGA) integration of the necessary baseband (BB) signal processing for some of the emergent highly efficient amplification architectures. Following the software-design radio concept, this design is aimed at generating, monitoring and correcting BB and intermediate frequency signals for operating in highly efficient power amplifier (PA) architectures, such as envelope tracking PAs, envelope elimination and restoration or polar transmitter and linear amplification with non-linear components. The closed-loop nature of this FPGA design allows introducing control strategies to overcome or mitigate the unwanted distortion arising from maladjustments in the aforementioned efficient transmitter architectures. In addition to the signal generation blocks, three key blocks are included in the design to significantly contribute to the performance of these power-efficient architectures. These three blocks are a fractional delay filter block, a block that generates a slower (or slew-rate-limited) version of the envelope of the signal and a digital adaptive predistortion block. Experimental results presented in this article show the importance of including these blocks to provide these efficient transmitter architectures with correcting capabilities to guarantee power efficiency and linear amplification at RF.

Published in:

Microwaves, Antennas & Propagation, IET  (Volume:5 ,  Issue: 8 )

Date of Publication:

June 6 2011

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