By Topic

Modeling of Layout Aware Line-Edge Roughness and Poly Optimization for Leakage Minimization

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Yongchan Ban ; Department of Electrical and Computer Engineering, University of Texas, Austin, TX, USA ; David Z. Pan

Line-edge roughness (LER) highly affects the device saturation current and leakage current, which leads to serious device performance degradation. In this paper, we propose the first layout-aware LER model where LER is highly related to the lithographic aerial image fidelity and neighboring geometric proximity. With our new LER model, we perform robust LER aware poly layout optimization to minimize the degradation of device performance, in particular leakage current. The results on 32-nm node standard cells show average 91.26% reduction of leakage current and 4.46% improvement of saturation current at the worst case process corner despite 8.86% area penalty.

Published in:

IEEE Journal on Emerging and Selected Topics in Circuits and Systems  (Volume:1 ,  Issue: 2 )