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On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM Cells

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12 Author(s)
Mazurier, J. ; Electron. & Inf. Technol. Lab., CEA-LE, Grenoble, France ; Weber, O. ; Andrieu, F. ; Toffoli, A.
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In this paper, an in-depth variability analysis, i.e., from the threshold voltage VT of metal-oxide-semiconductor field-effect-transistors (MOSFETs) to the static noise margin (SNM) of static random-access memory (SRAM) cells, is presented in fully depleted silicon-on-insulator (FDSOI) technology. The local VT variability σ(V)T lower than A(V)T = 1.4 mV · μm is demonstrated. We investigated how this good VT variability is reported on the SNM fluctuations σSNM at the SRAM circuit level. It is found experimentally that σSNM is correlated directly to the σ(V)T of SRAM transistors without any impact of the mean SNM value. The contributions of the individual MOSFETs in the SRAM cells have been determined quantitatively by using a homemade Simulation Program with Integrated Circuit Emphasis compact model calibrated on our FDSOI electrical characteristics. The VT variability in n-channel MOSFETs (nMOSFETs) is more critical than that in p-channel MOSFETs for SNM fluctuations, and σ(V)T in drive nMOSFETs is the key parameter to control for minimizing σSNM.

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Electron Devices, IEEE Transactions on  (Volume:58 ,  Issue: 8 )