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Impact of Hot Carriers on nMOSFET Variability in 45- and 65-nm CMOS Technologies

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8 Author(s)
Paolo Magnone ; Advanced Research Center on Electronic Systems, University of Bologna, Cesena, Italy ; Felice Crupi ; Nicole Wils ; Ruchil Jain
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This paper examines the impact of hot carriers (HCs) on n-channel metal-oxide-semiconductor (MOS) field-effect transistor mismatch across the 45- and 65-nm complementary MOS technology generations. The reported statistical analysis is based on a large overall sample population of about 1000 transistors. HC stress introduces a source of variability in device electrical parameters due to the randomly generated charge traps in the gate dielectric or at the substrate/dielectric interface. The evolution of the threshold-voltage mismatch during an HC stress is well modeled by assuming a Poisson distribution of the induced charge traps with a nonuniform generation along the channel. Once the evolution of the HC-induced VT shift is known, a single parameter is able to accurately describe the evolution of the HC-induced VT variability. This parameter is independent of the stress time and stress bias voltage. The HC stress causes a significantly larger degradation in the subthreshold slope variability, compared to threshold voltage variability for both investigated technology nodes.

Published in:

IEEE Transactions on Electron Devices  (Volume:58 ,  Issue: 8 )