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A 400-nW 19.5-fJ/Conversion-Step 8-ENOB 80-kS/s SAR ADC in 0.18- \mu\hbox {m} CMOS

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5 Author(s)
Jia Hao Cheong ; Institute of Microelectronics, Singapore ; Kok Lim Chan ; Pradeep Basappa Khannur ; Kei Tee Tiew
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As the low-power-consumption requirement of integrated circuits for biomedical applications (e.g., wearable sensor nodes operating with and without batteries, and implantable medical devices powered by batteries and wireless charging) becomes more stringent, the data converter design evolves toward mircrowatt and submircrowatt power consumption. In this brief, a 400-nW successive approximation analog-to-digital converter (SAR ADC) is presented. A trilevel switching scheme with common-mode reset, redundant algorithm, and a time-domain comparator is proposed and implemented to achieve ultralow power consumption. The redundant algorithm mitigates the offset error caused by the level mismatch of the trilevel switching scheme, whereas the trilevel switching scheme simplifies the switching logic of the redundant algorithm. Fabricated in a 0.18-μm CMOS process, the proposed SAR ADC achieves a signal-to-noise-and-distortion ratio of 50 dB, which is equivalent to an 8-bit effective number of bits, at an 80-kS/s conversion rate. The figure of merit is 19.5 fJ/conversion step.

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IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:58 ,  Issue: 7 )