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Dual-operating-voltage scheme for a single 5-V 16-Mbit DRAM

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8 Author(s)
Horiguchi, M. ; Hitachi Ltd., Tokyo, Japan ; Aoki, M. ; Tanaka, H. ; Etoh, Jun
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A dual-operating-voltage scheme (5 V for peripheral circuits and 3.3 V for the memory array) is shown to be the best approach for a single 5-V 16-Mb DRAM (dynamic random-access memory). This is because the conventional scaling rule cannot apply to DRAM design due to the inherent DRAM word-line boosting feature. A novel internal voltage generator to realize this approach is presented. Its features are the switching of two reference voltages, a driver using a PMOS-load differential amplifier, and the word-line boost based on the regulated voltage, which can ensure a wider memory margin than conventional circuits. This approach is applied to an experimental 16-Mb DRAM. A 0.5% supply-voltage dependency and 30-ns recovery time are achieved

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:23 ,  Issue: 5 )

Date of Publication:

Oct 1988

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