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A 60-ns 16-Mbit CMOS DRAM with a transposed data-line structure

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11 Author(s)
M. Aoki ; Hitachi Ltd., Tokyo, Japan ; Y. Nakagome ; M. Horiguchi ; H. Tanaka
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Low-noise, high-speed circuit techniques for high-density DRAMs (dynamic random-access memories), as well as their application to a single 5-V 16-Mb CMOS DRAM with a 3.3-V internal operating voltage for a memory array, are described. It was found that data-line interference noise becomes unacceptably high (more than 25% of the signal) and causes a serious problem in 16-Mb DRAM memory arrays. A transposed data-line structure is proposed to eliminate the noise. Noise suppression below 5% is confirmed using this transposed data-line structure. A current sense amplifier is also proposed to maintain the data-transmission speed in common I/O lines, in spite of a reduced operating voltage and increased parasitic capacitance loading in the memory array. A speed improvement of 10 ns is achieved. Using these circuit techniques, a 16-Mb CMOS DRAM with a typical RAS access time of 60 ns was realized

Published in:

IEEE Journal of Solid-State Circuits  (Volume:23 ,  Issue: 5 )