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A parallel architecture for arithmetic coding and its VLSI implementation

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4 Author(s)
Horng-Yeong Lee ; Dept. of Electron. Eng., Nat. Yunlin Inst. of Technol., Taiwan ; Leu-Shing Lan ; Ming-hwa Sheu ; Chien-Hsing Wu

A new parallel architecture for arithmetic coding is presented in this paper. By dividing the input symbols into a number of groups and processing them in parallel, significant speed-up can be achieved in comparison with existing architectures. The advantages of this parallel architecture are its easier expandability, higher speed, and smaller latency. The parallel arithmetic coder has also been implemented on VLSI using the VHDL technique. The resultant chip layout has a size of 4993×6503 μm2

Published in:

Circuits and Systems, 1996., IEEE 39th Midwest symposium on  (Volume:3 )

Date of Conference:

18-21 Aug 1996

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