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A 16-Mbit DRAM with a relaxed sense-amplifier-pitch open-bit-line architecture

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16 Author(s)
Inoue, M. ; Matsushita Electr. Ind. Co. Ltd., Moriguchi, Osaka, Japan ; Yamada, T. ; Kotani, H. ; Yamauchi, H.
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A 16-Mb dynamic RAM has been designed and fabricated using 0.5-μm CMOS technology with double-level metallization. It uses a novel trench-type surrounding high-capacitance cell (SCC) that measures only 3.3-μm2 in cell size with a 63-fF storage capacitance. A novel relaxed sense-amplifier-pitch (RSAP) open-bit-line architecture used on the DRAM achieves a high-density memory cell array, while maintaining a large enough layout pitch for the sense amplifier. These concepts allow the small chip that measures 5.4×17.38 (93.85) mm2 to be mounted in a 300-mil dual-in-line package with 65-ns RAS access time and 35-ns column address access time

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:23 ,  Issue: 5 )