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Proposed is a zero-inserting precoder and a two-stage linear equaliser, to shorten the guard interval in block-based single-carrier modulation. The first-stage equaliser consists of a linear single-tapper-subcarrier frequency-domain equaliser. The second-stage equaliser maximises the SINR, in the time-domain, based on the interference-plus-noise estimated from the zero-padded sub-intervals of the single-carrier modulation. This proposed scheme is applicable even without cyclic prefixing.
Date of Publication: June 23 2011