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Degradation of p-channel poly-Si thin-film transistors under dynamic negative bias temperature (NBT) stress has been studied. A two-stage degradation behavior is observed under the dynamic NBT stress. Device threshold voltage (Vth) shifts toward positive values in the first stage to more negative values in the second stage. The capacitance-voltage characteristic indicates a negative-charge generation in the gate oxide during the dynamic NBT stress, which is responsible for the positive Vth shift, while the well-known dc NBT instability effect causes the negative Vth shift. The dynamic effect is more significant under dynamic NBT stress with shorter pulse falling time and/or higher pulse amplitude. A degradation mechanism is proposed to explain the negative-charge generation under the dynamic NBT stress.