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A 0.31–1 GHz Fast-Corrected Duty-Cycle Corrector With Successive Approximation Register for DDR DRAM Applications

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7 Author(s)
Young-Jae Min ; Sch. of Electr. Eng., Korea Univ., Seoul, South Korea ; Chan-Hui Jeong ; Kyu-Young Kim ; Won Ho Choi
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This brief presents a duty cycle corrector (DCC) using a binary search algorithm with successive approximation register (SAR). The proposed DCC consists of a duty-cycle detector, a duty-cycle adjuster, its controller and an output buffer. In order to achieve fast duty-correction with a small die area, a SAR-controller is exploited as a duty-correction controller. The proposed DCC circuit has been implemented and fabricated in a 0.13-μm CMOS process and occupies 0.048 mm2. The measured duty-cycle error for the 50% duty-rate is below 1% (or 10 pS) within 320 pS external input duty-cycle error. The duty of output signal is corrected only with 14 cycles. This DCC operates from 312.5 MHz to 1 GHz and dissipates 3.2 mW at 1 GHz.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:20 ,  Issue: 8 )