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Validation of channel decoding ASIPs a case study

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4 Author(s)
Brehm, C. ; Microelectron. Syst. Design Res. Group, Univ. of Kaiserslautern, Kaiserslautern, Germany ; Wehn, N. ; Loitz, S. ; Kunz, W.

It is well known that validation and verification is the most time consuming step in complex System-on-Chip design. Thus, different validation and verification approaches and methodologies for various implementation styles have been devised and adopted by the industry. Application specific instruction set-processors (ASIPs) are an emerging implementation technology to solve the energy efficiency/flexibility trade-off in baseband processing for wireless communication where multiple standards have to be supported at a very low power budget and a small silicon footprint. In order to balance these contrary aims ASIPs for these application domains have a restricted functionality tailored to a specific class of algorithms compared to traditional ASIPs. Downside of the outstanding efficiency/flexibility ratio is the coincidence of bad attributes for validation. Compared to standard processors, these ASIPs often have a very complex instruction set architecture (ISA) due to the tight coupling between the instructions and the optimized micro-architecture requiring new validation concepts. This paper will sensitize for the distinctiveness and complexity of the validation of ASIPs tailored to channel decoding. In a case study a composite approach comprising formal methods as well as simulations and rapid-prototyping for validating an existing channel decoding ASIP is applied and transferred it into an industry product.

Published in:

Rapid System Prototyping (RSP), 2011 22nd IEEE International Symposium on

Date of Conference:

24-27 May 2011