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An experimental 1-Mbit CMOS SRAM with configurable organization and operation

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12 Author(s)
T. Williams ; IBM, Essex Junction, VT, USA ; K. Beilstein ; B. El-Kareh ; R. Flaker
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A 1-Mb SRAM (static random-access memory) configurable as a 128-kb×8, 256-kb×4, or 1-Mb×1 memory featuring asynchronous operation with static-column and chip-enable-access speedup modes or synchronous operation with a fast-page (toggle) or static-column mode is described. It has been fabricated in a double-metal, double-polysilicon CMOS process with 0.7-μm geometry and special SRAM structures. The measured synchronous access of 29 ns with a fast-page mode access of 22 ns. Measured asynchronous access is 34 ns with a static-column access of 33 ns and a chip-select speedup access of 29 ns. The SRAMs six-transistor CMOS memory cell is 58.24 μm2

Published in:

IEEE Journal of Solid-State Circuits  (Volume:23 ,  Issue: 5 )