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In this paper, the impact of interconnects' resistive losses upon the reliability of ULSI microchips has been studied. The experimentally measured signal waveforms at the far end of on-die (45-nm CMOS technology ULSI test chip) interconnects with different levels of resistive losses have been taken as a basis for calculations of Age parameters (from the Berkeley reliability tools model) of MOSFETs whose inputs are supplied with these signals. The results reveal that, with the growth of resistive losses, the degradation of the MOSFETs due to hot carrier injection (HCI) wearout mechanism is accelerated and their dynamic power consumption is augmented. Furthermore, it was found that, for applications where these MOSFETs are directly loaded by the following interconnection line, the electromigration and Joule heating of this line are aggravated (independently of the level of losses in the line), and degradation of MOSFETs (connected to the far end of the line) due to HCI is accelerated as well. Therefore, the interconnects' resistive losses are a serious reliability issue and should be taken into account in corresponding reliability models. Both measurements and simulations predict the aggravation of this phenomenon for future technologies.