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A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm

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2 Author(s)
Chao-Ching Hung ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Shen-Iuan Liu

A 40-GHz fast-locked all-digital phase-locked loop (ADPLL) using a modified bang-bang algorithm is presented. An inductor is used to extend the frequency tuning range of a 40-GHz digitally controlled oscillator. This ADPLL is fabricated by a 90-nm complementary metal-oxide-semiconductor process. The measured peak-to-peak jitter and the root-mean-square jitter are 2.622 ps and 303.632 fs, respectively, at 40 GHz. The measured locked times are 1.3 ms and 15 μs without and with the modified bang-bang algorithm, respectively.

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:58 ,  Issue: 6 )