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This paper describes a fast procedure for identifying undetectable transition faults under functional broadside tests. By using reachable states as scan-in states, functional broadside tests avoid overtesting that may occur when scan-based tests are used for detecting delay faults. The proposed procedure is based only on logic simulation, and does not perform test generation of any type. In one of its variations, the procedure uses logic simulation of fully unspecified primary input vectors starting from a known initial state in order to identify a superset of broadside tests that covers all the functional broadside tests. It then uses this superset to identify undetectable transition faults. The procedure identifies large numbers of undetectable transition faults in certain benchmark circuits.
Date of Publication: June 2012