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A 25-ns low-power full-CMOS 1-Mbit (128 K×8) SRAM

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8 Author(s)
S. T. Chu ; Philips Res. Lab., Eindhoven, Netherlands ; J. Dikken ; C. D. Hartgring ; F. J. List
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A 5-V full-CMOS 1-Mb SRAM (static random-access memory) is described. The access time is 25 ns with 30-pF load, and power dissipation is 75 mW at 10 MHz and less than 1 μW in standby mode. The chip is made in a 0.7-μm twin-tub, single-poly, double-metal technology on p/p+ epi substrate. Cascoding of NMOS devices and special timing techniques are used to suppress hot-electron degradation. The authors describe circuit techniques that obtain low active power dissipation and high speed for a byte-wide part

Published in:

IEEE Journal of Solid-State Circuits  (Volume:23 ,  Issue: 5 )