By Topic

A 25-ns low-power full-CMOS 1-Mbit (128 K×8) SRAM

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)
Chu, S.T. ; Philips Res. Lab., Eindhoven, Netherlands ; Dikken, J. ; Hartgring, C.D. ; List, F.J.
more authors

A 5-V full-CMOS 1-Mb SRAM (static random-access memory) is described. The access time is 25 ns with 30-pF load, and power dissipation is 75 mW at 10 MHz and less than 1 μW in standby mode. The chip is made in a 0.7-μm twin-tub, single-poly, double-metal technology on p/p+ epi substrate. Cascoding of NMOS devices and special timing techniques are used to suppress hot-electron degradation. The authors describe circuit techniques that obtain low active power dissipation and high speed for a byte-wide part

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:23 ,  Issue: 5 )