Referenced Items are not available for this document.
A 1-Mb (256 K×4 b) CMOS static random-access memory with a high-resistivity load cell was developed with 0.7-μm CMOS process technology. This SRAM achieved a high-speed access of 18 ns. The SRAM uses a three-phase back-bias generator, a bus level-equalizing circuit and a four-stage sense amplifier. A small 4.8×8.5-μm2 cell was realized by the use of a triple-polysilicon structure. The grounded second-polysilicon layer increases cell capacitance and suppresses α-particle-induced soft errors. The chip size measures 7.5×12 mm2
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:23
,
Issue:
5
)
Date of Publication: Oct 1988
- Page(s):
- 1073 - 1077
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 3309996
- Digital Object Identifier :
- 10.1109/4.5927
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Oct 1988
- Sponsored by :
- IEEE Solid-State Circuits Society
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