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An 8-ns 256K ECL SRAM with CMOS memory array and battery backup capability

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8 Author(s)
H. V. Tran ; Texas Instrum. Inc., Dallas, TX, USA ; D. B. Scott ; P. K. Fung ; R. H. Havemann
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The authors describe the first high-performance, high-density ECL SRAM (emitter-coupled-logic static random-access memory) compatible with battery backup techniques. The 256K device has a measured access time of 8 ns. Fabricated in a 0.8-μm BiCMOS process, the chip uses 117-μm 2, full-CMOS, six-transistor memory cells and measures 6.5×8.15 mm2. The design methodology described here illustrates the extent to which bipolar devices can be integrated into the periphery of a CMOS memory array. This integration was achieved through the use of a novel sensing scheme which provided three stages of bipolar differential sensing, with the first stage of sensing taking place directly on the bit lines

Published in:

IEEE Journal of Solid-State Circuits  (Volume:23 ,  Issue: 5 )