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Performance analysis of STC104 interconnection networks

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2 Author(s)
Hyo Jong Lee ; Dept. of Electron. Eng., Chonbuk Nat. Univ., Chonju, South Korea ; Byeong Yeol Song

The fast routing chip, Inmos STC104 has been designed and is now available in the market. Many research results concerning the performance, design cost and scalability of the packet switch have been presented and are currently under evaluation. There is a great demand for an efficient and reliable router in high performance parallel processing systems or data management networks. The performance and characteristics of each different network topology (e.g. multistage networks, meshes, tori, and N-cubes) are vital to make a decision on an appropriate network. The paper reviews the technology utilized in the fast packet switch, STC104 and studies reliable routing algorithms for various network configurations. The performance of each different configuration is also studied and compared

Published in:

High Performance Computing on the Information Superhighway, 1997. HPC Asia '97

Date of Conference:

28 Apr-2 May 1997

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