Referenced Items are not available for this document.
Parallel controllers can be best specified using a description with a formal support to validate structural and dynamic properties. Petri nets (PN) can provide an adequate means to model and to animate parallel systems based on the control and data path approach, in a hierarchically structured way. A set of tools was developed to allow formal validation of parallel controllers, based on hierarchical PN-based specifications and to automatically generate RT-level VHDL code. An example of a VLSI chip design, the transputer link adapter, shows the capabilities of this methodology and associated tools
Published in:
Computers and Digital Techniques, IEE Proceedings -
(Volume:144
,
Issue:
2
)
Date of Publication: Mar 1997
- Page(s):
- 127 - 137
- ISSN :
- 1350-2387
- INSPEC Accession Number:
- 5573494
- Digital Object Identifier :
- 10.1049/ip-cdt:19970845
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Mar 1997
- Sponsored by :
- IET
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