Referenced Items are not available for this document.
The authors present a custom chip for use in digital predistortion linearisation of RF power amplifiers. The chip is mainly implemented with systolic arrays. At maximum clock-rate, 130 MHz, the throughput is 16 Msamples/s with a 5 V supply voltage and power consumption of 1 W. A throughput of 2 Msamples/s is achieved at a 1.2 V supply voltage with 6 mW power consumption
Published in:
Electronics Letters
(Volume:33
,
Issue:
11
)
Date of Publication: 22 May 1997
- Page(s):
- 925 - 926
- ISSN :
- 0013-5194
- INSPEC Accession Number:
- 5597766
- Digital Object Identifier :
- 10.1049/el:19970660
- Date of Current Version :
- 06 August 2002
- Issue Date :
- 22 May 1997
- Sponsored by :
- Institution of Engineering and Technology
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
