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CMOS Technology Scaling Considerations for Multi-Gbps Optical Receivers With Integrated Photodetectors

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3 Author(s)
Anthony Chan Carusone ; Department of Electrical and Computer Engineering, University of Toronto, Toronto, Canada ; Hemesh Yasotharan ; Tony Kao

The integration of photodetectors for optical communication into standard nanoscale CMOS process technologies can enable low cost for emerging high volume short-reach parallel optical communication. Whereas past work has highlighted the challenges that face integrated photodetectors in highly scaled CMOS technologies, this work examines the opportunities afforded by these new technologies. First, scaling promises improved extrinsic photodetector bandwidth thanks to improved TIA performance. Second, modern advanced process features enable new photodetector structures with improved performance. A phototransistor employing deep n-wells is characterized in 65-nm CMOS and exhibits a more than ten-fold increase in responsivity over a similar structure without the buried n-well. Third, equalization techniques benefit from technology scaling and are only just beginning to be applied to CMOS integrated photodetectors. In particular, decision feedback equalization appears to offer potential for 10+ Gbps operation.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:46 ,  Issue: 8 )