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Detection of multiple faults in MOS circuits

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1 Author(s)
F. J. Ferguson ; Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA

Test sets that detect multiple faults in MOS circuits are characterized, guided by the observation that such circuits are implemented as networks of switches. This leads to a conceptually simple technique for generating multiple fault test sets. Sufficient conditions for the detection of all multiple faults are given for switch networks, and it is shown that a test set exists meeting these conditions for any irredundant circuit with certain restrictions on fan out. In the cases where these conditions cannot be met, a class of robust test sets is presented. Test sets that generate complete multiple fault test sets with fewer vectors for many MOS complex gates than is possible using a gate-level description of the circuit are presented

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:9 ,  Issue: 9 )