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The complexity of fault detection in MOS VLSI circuits

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2 Author(s)
Najm, F.N. ; Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA ; Hajj, I.N.

Consideration is given to the fault detection problem for a single fault in a single MOS channel-connected subcircuit. The following three decision subproblems are identified: (1) decide if a test vector exists, (2) decide if an initializing vector exists, and (3) decide if a test pair is robust. It is proven that each of these problems is NP-complete. More importantly, it is proved that the first two remain NP-complete for the simplest subcircuit design styles, namely series/parallel nMOS or CMOS logic gates. The third subproblem is shown to be of linear complexity for a CMOS logic gate with a stuck-open fault. It is illustrated that a test pair that is not robust may contain a robust subtest pair, and a necessary and sufficient condition for this to happen in CMOS logic gates is given. This leads to a linear time algorithm for CMOS logic gates which tests for robustness and, if possible, derives a robust test pair from a possibly nonrobust pair. The implications of these complexity results on practical transistor-level test generation tools are discussed

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:9 ,  Issue: 9 )