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Toward massively parallel automatic test generation

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3 Author(s)
S. T. Chakradhar ; Rutgers Univ., Piscataway, NJ, USA ; M. L. Bushnell ; V. D. Agrawal

A new automatic test pattern generation (ATPG) methodology that has the potential to exploit fine-grain parallel computing and relaxation techniques is described. This approach is radically different from the conventional methods used to generate tests for circuits from their gate level description. The digital circuit is represented as a bidirectional network of neurons. The circuit function is coded in the firing thresholds of neurons and the weights of interconnection links. This neural network is suitably reconfigured for solving the ATPG problem. A fault is injected into the neural network and an energy function is constructed with global minima at test vectors. The authors simulated the neural network on a serial computer, and determined the global minima of the energy function using a directed search technique augmented by probabilistic relaxation. Preliminary results on combinational circuits confirm the feasibility of this technique

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:9 ,  Issue: 9 )