By Topic

Incorporating bottom-up design into hardware synthesis

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
M. C. McFarland ; AT&T Bell Lab., Murray Hill, NJ, USA ; T. J. Kowalski

A novel method for using bottom-up design information in the synthesis of integrated circuits from abstract behavioral description is reported. There are two important ways in which this method differs from traditional top-down synthesis techniques. First, it draws on a newly developed procedural database to collect detailed information on the physical and logical properties of the primitives available for building the design. Second, it partitions each design it considers into clusters that have physical as well as logical significance. This method for representing and organizing knowledge about candidate designs makes it possible to estimate physical placement and wiring, even at the abstract register-transfer (RT) level. This allows a more accurate evaluation of RT designs without doing a full logic-level or transistor-level layout. Partitioning also leads to a simple method for systematically exploring the space of possible designs to find the one that best meets the designer's objectives and constraints

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:9 ,  Issue: 9 )