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Incorporating bottom-up design into hardware synthesis

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2 Author(s)
McFarland, Michael C. ; AT&T Bell Lab., Murray Hill, NJ, USA ; Kowalski, Thaddeus J.

A novel method for using bottom-up design information in the synthesis of integrated circuits from abstract behavioral description is reported. There are two important ways in which this method differs from traditional top-down synthesis techniques. First, it draws on a newly developed procedural database to collect detailed information on the physical and logical properties of the primitives available for building the design. Second, it partitions each design it considers into clusters that have physical as well as logical significance. This method for representing and organizing knowledge about candidate designs makes it possible to estimate physical placement and wiring, even at the abstract register-transfer (RT) level. This allows a more accurate evaluation of RT designs without doing a full logic-level or transistor-level layout. Partitioning also leads to a simple method for systematically exploring the space of possible designs to find the one that best meets the designer's objectives and constraints

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:9 ,  Issue: 9 )